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author | David Robillard <d@drobilla.net> | 2019-12-08 19:44:06 +0100 |
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committer | David Robillard <d@drobilla.net> | 2019-12-08 21:08:26 +0100 |
commit | 9b0da6ca2d5533261be3c88bcbfd948a81df3fc7 (patch) | |
tree | 38ff2d66771a13bdb7d4b64cf942e9d9ead44687 /src/server | |
parent | 3a59f2d385e9a9bcc6fb939a4df6380c27f4d2ff (diff) | |
download | ingen-9b0da6ca2d5533261be3c88bcbfd948a81df3fc7.tar.gz ingen-9b0da6ca2d5533261be3c88bcbfd948a81df3fc7.tar.bz2 ingen-9b0da6ca2d5533261be3c88bcbfd948a81df3fc7.zip |
Cleanup: Remove multiple variable declarations on a single line
Diffstat (limited to 'src/server')
-rw-r--r-- | src/server/ControlBindings.cpp | 9 | ||||
-rw-r--r-- | src/server/events/Delta.cpp | 6 |
2 files changed, 11 insertions, 4 deletions
diff --git a/src/server/ControlBindings.cpp b/src/server/ControlBindings.cpp index 51784452..3e123a16 100644 --- a/src/server/ControlBindings.cpp +++ b/src/server/ControlBindings.cpp @@ -253,7 +253,8 @@ ControlBindings::control_to_port_value(RunContext& context, normal = (expf(normal) - 1.0f) / ((float)M_E - 1.0f); } - float min, max; + float min = 0.0f; + float max = 1.0f; get_range(context, port, &min, &max); return normal * (max - min) + min; @@ -269,7 +270,8 @@ ControlBindings::port_value_to_control(RunContext& context, return 0; } - float min, max; + float min = 0.0f; + float max = 1.0f; get_range(context, port, &min, &max); const float value = value_atom.get<float>(); @@ -337,7 +339,8 @@ ControlBindings::set_port_value(RunContext& context, Type type, int16_t value) { - float min, max; + float min = 0.0f; + float max = 1.0f; get_range(context, port, &min, &max); const float val = control_to_port_value(context, port, type, value); diff --git a/src/server/events/Delta.cpp b/src/server/events/Delta.cpp index 31f55306..3fb60bfe 100644 --- a/src/server/events/Delta.cpp +++ b/src/server/events/Delta.cpp @@ -224,7 +224,11 @@ Delta::pre_process(PreProcessContext& ctx) if (is_graph_object && !_object) { Raul::Path path(uri_to_path(_subject)); - bool is_graph = false, is_block = false, is_port = false, is_output = false; + + bool is_graph = false; + bool is_block = false; + bool is_port = false; + bool is_output = false; ingen::Resource::type(uris, _properties, is_graph, is_block, is_port, is_output); if (is_graph) { |