From f5f4e7f081c9fbbe3b63ba72cdc12489653fb1bf Mon Sep 17 00:00:00 2001 From: David Robillard Date: Sat, 28 Apr 2012 05:28:50 +0000 Subject: Use CV ports on internal modules. git-svn-id: http://svn.drobilla.net/lad/trunk/ingen@4301 a436a847-0d15-0410-975c-d299462d15a1 --- src/server/internals/Trigger.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/server/internals/Trigger.cpp') diff --git a/src/server/internals/Trigger.cpp b/src/server/internals/Trigger.cpp index 15921ae9..d6d13c58 100644 --- a/src/server/internals/Trigger.cpp +++ b/src/server/internals/Trigger.cpp @@ -71,19 +71,19 @@ TriggerNode::TriggerNode( _ports->at(1) = _note_port; _gate_port = new OutputPort(bufs, this, "gate", 2, 1, - PortType::AUDIO, 0, bufs.forge().make(0.0f)); + PortType::CV, 0, bufs.forge().make(0.0f)); _gate_port->set_property(uris.lv2_portProperty, uris.lv2_toggled); _gate_port->set_property(uris.lv2_name, bufs.forge().alloc("Gate")); _ports->at(2) = _gate_port; _trig_port = new OutputPort(bufs, this, "trigger", 3, 1, - PortType::AUDIO, 0, bufs.forge().make(0.0f)); + PortType::CV, 0, bufs.forge().make(0.0f)); _trig_port->set_property(uris.lv2_portProperty, uris.lv2_toggled); _trig_port->set_property(uris.lv2_name, bufs.forge().alloc("Trigger")); _ports->at(3) = _trig_port; _vel_port = new OutputPort(bufs, this, "velocity", 4, 1, - PortType::AUDIO, 0, bufs.forge().make(0.0f)); + PortType::CV, 0, bufs.forge().make(0.0f)); _vel_port->set_property(uris.lv2_minimum, bufs.forge().make(0.0f)); _vel_port->set_property(uris.lv2_maximum, bufs.forge().make(1.0f)); _vel_port->set_property(uris.lv2_name, bufs.forge().alloc("Velocity")); -- cgit v1.2.1